It is conventional in integrated circuit processing that the fabrication processes are continually being improved to reduce the geometry sizes, enhance device properties and lower production costs. There are many changes that cannot be made to all components of the circuit, so that a uniform size change for all components, referred to as a uniform shrink, does not give an optimum size reduction. In that case, each circuit must be changed by hand, which is extremely expensive and takes a long time. It is not possible, therefore, to implement improvements when they become available. It is necessary to wait until the benefit from making a change outweighs the costs of making it.
The conventional way of making a nonuniform shrink is the use of a "symbolic layout", in which schematic symbols representing components of the devices, such as the implant area for a transistor, the gate electrode, the vias, etc., are associated with a geometric size or shape, so that it is possible to convert from the pictorial representation of the layout to the coordinate numbers used to drive the automatic machinery that makes a mask.
In conventional practice, each cell of a set of logic cells for a gate array is converted individually and "by hand", either on paper or on a CAD system. A set of reference points, referred to as grid points, is defined for each cell, covering each mask element (each individual area that is defined on a mask) in the cell. The old circuit design is changed according to the new design rules and each mask element of the logic cell is adjusted in position. This process is repeated manually for each cell in the cell library. Errors are made in the conversion process, of course, and time is required to locate and correct the errors.
The industry has felt the need to make a nonuniform shrink in as automated a fashion as possible, not only to increase the speed of the transformation, but also to eliminate human errors in the conversion process.
This invention takes advantage of the fact that for gate array cells (as opposed to "custom" circuits or random logic), the mask/layout geometries differ only on the interconnect or "personalization" layers and the metal interconnect (contacts and vias) layers. All other layers, for example, field implant, diffusion and polysilicon are the same for every gate array cell. This means that any changes that must be made to these other layers affect all cells in the same way.
The invention also takes advantage of the fact that certain parameters, such as metal width or polysilicon width, are the same for all cells. These parameters may be represented "symbolically". This is a common simplification and when used, it is known as "symbolic layout".